1. Field of the Invention
The present invention relates to an optical sensor array, and more particularly to an optical sensor array which uses a thick amorphous silicon film which constitutes a light dependent variable resistance element as an optical sensor element.
2. Description of the Related Art
As an optical sensor which has been used popularly, there has been known an optical sensor which adopts a method where a reverse bias is applied to crystalline silicon (Si) or a so-called pn junction of a semiconductor thus using a depletion layer as a junction capacitance, and a pair of electron and hole which are subjected to photoelectric conversion is separated, and a charge is held or taken out through the depletion layer (JP 2008-251609 A (patent document 1)). This optical sensor is schematically shown in FIG. 11A to FIG. 11D.
FIG. 11A shows an equivalent circuit in a simplified manner. In FIG. 11A, symbol PD indicates a photo diode, symbols S1, S2 indicate switches, symbol DET indicates a detection mechanism, and symbol Va indicates a power source.
Here, the photo diode PD is a depletion layer capacitance part where a reverse bias is applied to the pn junction, wherein a photoelectric charge pair which is generated in a semiconductor layer by an incident light is separated and a charge is stored as an effective charge. The stored photo charge is read by a switch S1 at certain timing, and is detected as a quantity of charge dependent on a light quantity by the detection mechanism DET. When the reading of the stored photo charge is finished, a predetermined reverse bias is applied to the photo diode PD from the power source Va by operations of switches S1, S2 so that initial setting is performed whereby the photo charge is stored in the photo diode PD again.
FIG. 11B, FIG. 11C and FIG. 11D show constitutional examples of the pn junction which constitutes the photo diode PD, wherein FIG. 11B shows the constitutional example where a depletion layer capacitance is generated longitudinally, FIG. 11C shows the constitutional example where a depletion layer capacitance is generated laterally, and FIG. 11D shows a constitutional example which is referred to as PIN. Here, as has been well-known, in FIG. 11B, FIG. 11C and FIG. 11D, symbol p indicates a p-type region, symbol n indicates an n-type region, and symbol I indicates an insulation layer.